1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a semiconductor device which internally generates a necessary voltage. In particular, the present invention relates to a structure for stably generating an internal voltage under a low power supply voltage level.
2. Description of the Background Art
With development and prevalence of communication and information processing equipments, various semiconductor devices are employed in those equipments. Higher performance is required for such semiconductor devices, while integrity in specification between components is becoming important since the semiconductor device is mounted on a board together with other devices and components. One example of the specification requiring the consistency is a voltage supplied to a plurality of semiconductor devices (components). If all of the devices and components operate with a common voltage, design of a power supply on the board is simplified. Therefore, one semiconductor chip (device) is basically required to operate receiving one kind of supply voltage (except for ground voltage).
However, a voltage having the same voltage level as that of external supply voltage extVdd is not always available as for a voltage supplied to a circuit within the semiconductor device (chip). As the operating speed and integration are advanced, a transistor is considerably decreased in dimension. In the case of MOS transistor (insulated gate field effect transistor), for example, external supply voltage extVdd is too high in view of the reliability of a gate insulating film and the breakdown voltage between the drain and source, and thus cannot directly be used for driving the MOS transistor. Accordingly, external supply voltage extVdd is internally converted to a required voltage level for application to an internal circuit.
FIG. 13 illustrates a structure of a conventional internal voltage down converter VDC. Referring to FIG. 13, internal voltage down converter VDC includes a comparator CMP for comparing a reference voltage Vrefs with an internal (power supply) voltage Vdds, and a current drive transistor DR for supplying current from an external power supply node to an internal voltage line according to an output signal of comparator CMP.
Comparator CMP includes p channel MOS transistors Q1 and Q2 coupled to the external supply node to supply current, n channel MOS transistors Q3 and Q4 receiving current from MOS transistors Q1 and Q2 to compare reference voltage Vrefs with internal voltage Vdds, and an n channel MOS transistor Q5 providing a path for causing an operating current flow through comparator CMP in response to an activation signal VDCON. MOS transistor Q2 has its gate and drain connected together to the gate of MOS transistors Q1, and MOS transistors Q1 and Q2 constitute a current mirror circuit.
Current drive transistor DR is constituted of a p channel MOS transistor.
In the structure of internal voltage down converter VDC shown in FIG. 13, when activation signal VDCON is at an L (logical low) level, MOS transistor Q5 is in OFF state, an output signal of comparator CMP is at the level of external supply voltage extVdd, and accordingly current drive transistor DR is in OFF state.
When activation signal VDCON attains an H (logical high) level, MOS transistor Q5 attains ON state and comparator CMP responsively starts a comparing operation. When internal voltage Vdds is higher than reference voltage Vrefs, an output signal of comparator CMP attains H level so that current drive transistor DR maintains OFF state. When internal voltage Vdds is lower than reference voltage Vrefs, an output signal of comparator CMP lowers so that current drive transistor DR supplies current from the external supply node to the internal voltage line according to the output signal of comparator CMP. As a result, the voltage level of internal voltage Vdds rises. Internal voltage Vdds is thus maintained at the level of reference voltage Vrefs.
Internal voltage Vdds from internal voltage down converter VDC is at the same level as that of reference voltage Vrefs and lower than external supply voltage extVdd, and is supplied to an internal circuit as an operating supply voltage, for example.
Concerning such internal voltage, there are a plurality of kinds in most cases. In a semiconductor memory device, for example, there are two kinds of internal voltages, or the voltage transmitted to a memory array and the voltage for operating peripheral circuitry. Voltage of a required intermediate level is also generated by a voltage down converter as shown in FIG. 13. Among these internal voltages, a voltage Vrl at a relatively low voltage level is usually used for reducing current consumption.
FIG. 14A illustrates one example of the usage of voltage Vrl. In FIG. 14A, voltage Vrl is utilized for adjusting an amount of current driven by a current source transistor Q6 of an internal circuit NK. If the level of voltage Vrl is low, the conductance of current source transistor Q6 is also small so that through current Ic in internal circuit NK can be reduced. In other words, standby current flowing in a standby state can be decreased and accordingly, battery-driven equipments can be operated for a long period of time with one battery.
FIG. 14B illustrates another usage of internal voltage Vrl. In the structure shown in FIG. 14B, transmission gates TG1 and TG2 are selectively set into conductive state by switch signal HS to supply one of internal voltages Vh and Vrl to the gate of current drive transistor Q6. Internal voltage Vh is higher than internal voltage Vrl.
When switch signal HS is at L level, an output signal of an inverter IV1 attains H level, and responsively transmission gate TG1 becomes conductive and internal voltage Vh is supplied to the gate of current drive transistor Q6. At this time, operating current (through current) Ic of internal circuit NK increases to allow internal circuit NK to operate at a high speed. On the other hand, when switch signal HS is at H level, an output signal of inverter IV1 falls to L level, and responsively transmission gate TG2 becomes conductive and internal voltage Vrl is supplied to the gate of current drive transistor Q6 and through current Ic is decreased.
According to the structure shown in FIG. 14B, the amount of current driven by current source drive transistor Q6 is adjusted according to an operation mode so as to decrease current consumption in the standby state and to implement a circuit operating at a high speed. Since through current Ic is changed depending on the operation mode switch signal HS, it is unnecessary to place a plurality of current source transistors and set these transistors selectively into ON state according to the operation mode. Consequently, the number of current source transistors can be decreased to reduce the area occupied by the entire circuit.
FIG. 15A illustrates a further usage of internal voltage Vrl. In the structure shown in FIG. 15A, internal voltage Vrl is supplied to the source of an n channel MOS transistor Q7. The drain of MOS transistor Q7 is coupled to receive a supply voltage Vd. Ground voltage GND is supplied to the gate of MOS transistor Q7. Internal voltage Vrl is a positive voltage and the gate-source voltage Vgs of the MOS transistor is negative, reducing leakage current (subthreshold current) Ioff. In this case, if back gate bias of MOS transistor Q7 is lower than internal voltage Vrl applied to the source thereof, substrate-source voltage Vbs increases in a negative direction and the threshold voltage of MOS transistor Q7 increases owing to the back gate bias effect. Accordingly, subthreshold current ioff can further be decreased.
The voltage application system illustrated in FIG. 15A is applied to a memory cell of a DRAM (Dynamic Random Access Memory). The voltage application scheme for decreasing the leakage current is referred to as Boosted Sense Ground (BSG) scheme as discussed by Asakura et al. in ISSCC, Digest of Technical Papers, 1994, pp. 1303-1309.
FIG. 15B illustrates voltage application to a memory cell according to the BSG scheme. Memory cell MC includes a memory capacitor Ms for storing information, and an access transistor MT for connecting a memory capacitor Ms to a bit line BL (or /BL) according to a signal voltage on a word line WL. Access transistor MT is constituted of an n channel MOS transistor, and has its gate connected to word line WL, its drain connected to bit line BL (or/BL) and its back gate receiving a constant bias voltage Vbb.
In a standby cycle, bit line BL is maintained at an intermediate voltage level and word line WL is at ground voltage GND level. Suppose that an active cycle now starts a memory cell is selected, and L level data is transmitted to bit line BL. If memory cell MC is a non-selected memory cell, the voltage on word line WL is at ground voltage GND level. Therefore, if voltage Vbsg corresponding to L level data on bit line BL is at internal voltage Vrl level, gate-source voltage Vgs of access transistor MT is a negative voltage. Further, the difference between back gate voltage Vbb of access transistor MT and voltage Vbsg on bit line BL increases in a negative direction so that leakage current flowing from memory capacitor Ms to bit line BL via access transistor MT is decreased. In other words, in the active cycle, reduction in voltage level of H level data in the non-selected memory cell is avoided, refresh characteristics are improved, and data holding time can be increased.
Utilization of such low level internal voltage Vrl is indispensable for achieving low current consumption of a semiconductor device. However, it is difficult to stably generate a voltage that is close to the threshold voltage of an n channel MOS transistor as internal voltage Vrl. For example, when n channel MOS transistor is diode-connected to generate internal voltage Vrl, the level of internal voltage Vrl changes according to the temperature characteristics of the threshold voltage of the MOS transistor, leading to a significant temperature dependency of internal voltage Vrl. In order to avoid this problem of temperature dependency, the voltage down converter as shown in FIG. 13 is employed, for example. In this case, reference voltages Vrefs and Vdds correspond to the voltage close to the threshold voltages of MOS transistors Q3 and Q4. The common source node of MOS transistors Q3 and Q4 is connected to the ground node via MOS transistor Q5. The common source node of these MOS transistors Q3 and Q4 is at a voltage level higher than the ground voltage due to the channel resistance of MOS transistor Q5. Even if the voltage at a level close to the threshold voltages of MOS transistors Q3 and Q4 is supplied to the gates of MOS transistors Q3 and Q4, MOS transistors Q3 and Q4 are substantially in OFF state and cannot perform a comparing operation.
FIG. 16 illustrates one example of the structure of a conventional Vrl generating circuit. Referring to FIG. 16, the Vrl generating circuit includes a p channel MOS transistor Q10 connected between an external supply node and a node NA and receiving ground voltage GND at its gate, a p channel MOS transistor Q11 connected between node NA and a node NB and receiving a reference voltage Vr10 at its gate, a p channel MOS transistor Q12 connected between node NA and a node NC and receiving the internal voltage Vrl at its gate, an n channel MOS transistor Q13 connected between node NB and a ground node and having its gate connected to node NB, and an n channel MOS transistor Q14 connected between node NC and the ground node and having its gate connected to node NB. MOS transistor Q13 and Q14 constitute a current mirror circuit.
In the structure shown in FIG. 16, when internal voltage Vrl is higher than reference voltage Vr10, the current flowing through MOS transistor Q11 is greater in amount than the current flowing through MOS transistor Q12. MOS transistors Q13 and Q14 allow current to flow therethrough which is the same in magnitude as the current flowing through MOS transistor Q11. Accordingly, the voltage level of node NC, i.e. the voltage level of internal voltage Vrl decreases.
On the contrary, when internal voltage Vrl is lower than reference voltage Vr10, the current flowing through MOS transistor Q12 is greater in amount than the current flowing through MOS transistor Q11. MOS transistor Q14 cannot discharge all the current supplied from MOS transistor Q12, and the level of internal voltage Vrl from node NC increases.
In other words, internal voltage Vrl is maintained at the level of reference voltage Vr10.
According to the structure of the Vrl generating circuit shown in FIG. 16, internal voltage Vrl is generated by the source current of MOS transistor Q12. Therefore, through current Ica of the Vrl generating circuit has to be increased. Especially, if internal voltage Vrl is used for a DRAM of the BSG scheme as shown in FIG. 15B, internal voltage Vrl is used for discharging the bit lines and thus a great current driving capability is required for the internal voltage generating circuit (in order to prevent increase of the voltage level of internal voltage Vrl due to discharging current). In the case of the structure shown in FIG. 16, the MOS transistor of a component should be increased in size (the ratio between the gate width and the gate length), leading to increase in the circuit occupation area and increase in current consumption.
FIG. 17 illustrates another structure of the conventional Vrl generating circuit. The Vrl generating circuit shown in FIG. 17 includes a comparator CMPP for comparing reference voltage Vr10 with internal voltage Vrl on an internal voltage line INV, and a current drive transistor NQ for discharging internal voltage line INV to a ground voltage level according to an output signal of comparator CMPP. Current drive transistor NQ is constituted of an n channel MOS transistor.
Comparator CMPP includes a p channel MOS transistor Q15 connected between an external supply node and an internal node ND and having its gate connected to a ground node, a p channel MOS transistor Q16 connected between internal node ND and an internal node NE and having its gate receiving reference voltage Vrl0, a p channel MOS transistor Q17 connected between internal node ND and an internal node NF and having its gate connected to internal voltage line INV, an n channel MOS transistor Q18 connected between internal node NE and the ground node and having its gate connected to internal node NF, and an n channel MOS transistor Q19 connected between internal node NF and the ground node and having its gate connected to internal node NF.
Comparator CMPP shown in FIG. 17 is equivalent to comparator shown in FIG. 13 with voltage polarity and conductivity types of transistors reversed. If internal voltage Vrl is higher than reference voltage Vrl0, the current flowing through MOS transistor Q17 is smaller in amount than the current flowing through MOS transistor Q16. MOS transistors Q18 and Q19 constitute a current mirror circuit and thus current of the same magnitude flows through MOS transistors Q18 and Q19. Consequently, an output signal from comparator CMPP attains a high level and the conductance of current drive transistor NQ increases so that current is discharged from internal voltage line INV to the ground node to decrease the voltage level of internal voltage Vrl. On the other hand, if internal voltage Vrl is lower than reference voltage Vrl0, an output signal of comparator CMPP is at L level to turn off current drive transistor NQ.
In the structure of the Vrl generating circuit shown in FIG. 17, if the speed of response to change in internal voltage Vrl is placed out of consideration, DC-wise current supplying capability can be increased by decreasing through current Icb while increasing the ratio between the channel width and the channel length of current drive transistor NQ for enhancing the current driving-power thereof, without increase in the occupying area. However, in view of an allowable range of change in internal voltage Vrl, the necessary minimum speed of response to internal voltage Vrl is required, and through current Icb is required to have a certain magnitude.
Utilization of the Vrl generating circuit as shown in FIG. 17 enables internal voltage Vrl having a great current supplying ability generation of with a small occupation area. However, in comparator CMPP, reference voltage Vrl0 and internal voltage Vrl are compared by p channel MOS transistors Q16 and Q17. The sources of MOS transistors Q16 and Q17 correspond to node ND. The current driving power of p channel MOS transistor Q17 is determined by gate-source voltage Vgs thereof. If external supply voltage extVdd transmitted to node ND changes, the current flowing through MOS transistors Q16 and Q17 changes in proportion to the square of the difference between gate-source voltage Vgs of MOS transistors Q16 and 17 and the threshold voltage thereof (MOS transistors Q16 and Q17 operate in a saturation region). Therefore, the level of internal voltage Vrl cannot be maintained at reference voltage Vrl0 level in a stable manner so that the level of internal voltage Vrl changes according to external supply voltage extVdd.
In order to solve the problem of power supply noise of external supply voltage extvdd, another internal voltage Vdd' might be used which is in a stable state even when internal voltage Vrl is consumed. However, another circuit for generating internal voltage Vdd' should be provided only for the stable operation of internal voltage Vrl, leading to increase in the circuit area.